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Silicon Photonics & Photonic AI investment tracker

Photonic AI — Current Development Stages

3 parallel layers · TRL 1–9

Layer 1 — Interconnect

TRL 8–9 / 9Commercial · At scale
Rack-to-rack fiber opticTRL 9
Co-packaged optics (CPO)TRL 8–9
Chip-to-chip opticalTRL 7–8
Board-level opticalTRL 6–7
2026 (Now)

1.6T transceivers entering volume deployment at hyperscalers. CPO at 51.2 Tb/s switches now standard in new datacenter builds. NVIDIA, Google, Amazon, and Microsoft committed to optical I/O-first architectures through 2028 capex cycles.

Mar 2025

NVIDIA Spectrum-X Co-Packaged Optics launched (TSMC, Coherent, Corning, Lumentum consortium). Direct photonic connection to chipset — 3.5× electrical efficiency, 4× fewer lasers, 63× better signal integrity.

2026–2027

Lightmatter Passage L200/L200X entering customer chip integration in 2026 via GlobalFoundries, ASE, and Amkor; production systems targeted for 2027. Celestial AI photonic fabric in customer evaluation. Photonic interposer connecting GPU clusters at rack scale — targeting 1 Pb/s aggregate bandwidth.

2027–2030

Board-to-board optical inside servers — CPU/GPU boards connected directly via fiber, eliminating electrical signaling at board level. Si₃N₄ optical backplanes targeted.

Layer 2 — Photonic Switch

TRL 6–8 / 9Early commercial · Scaling
ASIC + CPO switchTRL 8
Fully photonic switchTRL 6–7
Photonic AI-optimised switchTRL 4–5
2026 (Now)

ASIC + CPO switches now at third-generation CPO: Broadcom shipped Tomahawk 6 – Davisson (102.4 Tb/s CPO) in October 2025, doubling the bandwidth of Tomahawk 5 (51.2 Tb/s). Marvell Teralynx 10 remains in production deployment. CPO is now economically preferred over pluggables at hyperscale density. AMD acquired Enosemi (May 2025) to accelerate photonic interconnect manufacturing.

2025–2026

IPRONICS ONE and Lumentum fully photonic switch PICs sampling to Tier 1 OEMs. Photon routing instead of electron routing — sub-nanosecond switching latency demonstrated in lab.

2027–2030

Photonic AI switch becomes standard in hyperscale spine/leaf architecture. AI-optimised optical flow steering — major reduction in inter-server latency and network power consumption.

Layer 3 — Photonic Processor

TRL 3–5 / 9Research · Pre-production
Matrix multiply (ONN)TRL 5
Full DNN on single chipTRL 4–5
Programmable processorTRL 3–4
Production-ready chipTRL 2–3
Dec 2024

MIT executes a full DNN entirely in the optical domain (Nature Photonics). First single chip running a deep neural network purely in light with no mid-layer electronic conversion — the most important proof-of-concept of the decade.

2024

Taichi chip — 160 TOPS/W (Science 2024). Large-scale photonic chiplet achieves 160 TOPS/W, 50–160× more efficient than current GPUs. Runs image recognition. Lab chip with peer-reviewed performance.

2025

LightIn — programmable photonic processor (arXiv). 40 MZI programmable unit cells, 3.8×3 mm². Runs matrix multiply, image recognition, channel switching, and PUF security on one chip.

2025

64×64 photonic accelerator — 1 GHz MAC, 7.61-bit precision (Nature). 65nm SiPh + 28nm CMOS co-packaged, 16,000+ photonic components. Runs max-cut optimization.

2026 (Now)

Celestial AI in A/B customer tape-outs. No production silicon yet — still pre-revenue. EO polymer modulators (LWLG) and TFLN platforms at pilot-scale validation for 200Gbaud+ applications.

2027–2030

First production photonic AI accelerators for inference-specific niche workloads. Lightmatter Passage and Celestial AI targeting early revenue at specialized HPC/AI deployments.

2030+

Photonic TPU in hyperscale AI datacenters — the ultimate goal. Silicon-photonic AI accelerators standard for bandwidth-bound training and inference at scale.

Technical challenges

Precision limited to 7–8 bit

Versus GPU 16–32 bit. Sufficient for inference workloads, not yet sufficient for large LLM training.

Noise accumulation

Builds across multiple waveguide layers — requires continuous calibration that is difficult to automate at scale.

Analog-digital conversion overhead

Each optical-to-electrical conversion consumes power, eroding the efficiency advantage. Many benchmark figures measure only the optical portion, excluding ADC, laser source, and electronic control.

Upcoming Catalysts

earningsAug 12, 2026

COHR Q4 FY2026 Earnings

800G/1.6T transceiver ramp and InP vertical integration margin update

earningsAug 27, 2026

MRVL Q2 FY2027 Earnings

Teralynx 10 CPO volume shipments and Celestial AI custom silicon progress

earningsSep 2, 2026

AVGO Q3 FY2026 Earnings

AI ASIC revenue cadence, CPO deployment volumes, and 1.6T switch pipeline update

conferenceSep 20–24, 2026

ECOC 2026 Conference

52nd European Conference on Optical Communications, Málaga, Spain — 1.6T/3.2T standards, TFLN commercialization updates

milestone2026-Q3

1.6T Transceiver Volume Ramp

Hyperscaler volume deployments of 1.6T transceivers; key revenue inflection for optical manufacturers

earnings~Nov 2026

LITE Q1 FY2027 Earnings

ROADMs and pump laser shipment growth; 3.2T coherent design-win update. Exact date not yet announced — estimated from prior-year cadence.

milestone2026-Q4

POET Volume Production Milestone

POET optical interposer volume shipment ramp via DenseLight/POET Singapore partnership

milestone2026-Q4

LWLG Strategic Partnership

EO polymer commercialization agreement with Tier 1 component supplier expected

conferenceMar 7–11, 2027

OFC 2027 Conference

Optical Fiber Conference, Los Angeles — next-gen CPO architectures, EOP modulators, and fully photonic processor previews

Disclaimer: This is research commentary, not financial advice. All investments carry risk.

Last reviewed: August 2026