SiPh Supply Chain

Silicon photonics doesn't have its own supply chain — it inherits one from the $700B silicon IC industry, then adds a thin layer of photonic-specific materials and processes on top. That inheritance is both a strength and a vulnerability: world-class CMOS infrastructure is available, but photonic-specific inputs (InP substrates, germanium epitaxy, thin-film lithium niobate) sit at the end of extremely concentrated supply lines.

This page maps the six layers of the SiPh supply chain, from raw materials to emerging platforms, highlighting where concentration creates risk and which players control each chokepoint.

Supply chain overview

1

Raw Materials

InP

Laser substrate · Critical supply

SiO₂/Si

Waveguide platform · Low risk

LiNbO₃

Modulator material · High risk

Germanium

Photodetector · High risk

GaAs

VCSEL substrate · Medium risk

Si₃N₄

Passive waveguide · Low risk

2

Substrate & Wafer Production

AXT Inc (AXTI)

InP & GaAs wafers

Sumitomo Electric

InP substrates (JPN)

Soitec

Silicon-on-Insulator (FRA)

Shin-Etsu

SOI wafers (JPN)

3

Photonic Foundry

Tower Semi (TSEM)

SiPh 300mm platform

GlobalFoundries (GFS)

45RFSOI SiPh node

TSMC

SiPh + advanced packaging

Intel Foundry

Photonic integration layer

4

Photonic Integration

Coherent Corp (COHR)

InP lasers + transceivers

Lumentum (LITE)

EML lasers, ROADMs

MACOM (MTSI)

III-V analog photonics

POET Technologies (POET)

Optical interposer platform

5

CPO Packaging

Fabrinet (FN)

Optical contract manufacturing

TSMC COUPE

Co-packaged optics platform

Ayar Labs

TeraPHY optical I/O chiplet

6

Systems & Hyperscalers

Broadcom (AVGO)

CPO switch ASICs

Marvell (MRVL)

CPO + custom AI silicon

Ciena / Infinera

Optical transport systems

Google / AWS / Azure

AI datacenter deployment

Supply chain layers — click to expand

Structural bottlenecks

InP substrate duopoly

AXT (USA) and Sumitomo Electric (Japan) control InP wafer supply globally. No new capacity expansion has been announced. Indium is a byproduct of zinc smelting — supply cannot be ramped on a chip-fab timeline.

Germanium / Gallium export controls

China controls ~98% of global gallium production and ~68% of germanium refining — both essential for III-V semiconductors and fiber-optic components. Beijing has escalated this leverage in three steps:

  • August 2023: Export licensing requirements for Ge & Ga take effect, immediately halting shipments. Gallium prices more than doubled within months.
  • December 2024: China upgrades to an outright ban on Ge, Ga, and antimony exports to the US, alongside tighter graphite controls.
  • March 2026: The US-specific ban is suspended until November 2026 amid trade negotiations — but the legal framework remains intact and can be reinstated at any time.

The suspension is not a resolution. US trade data shows ~26% of germanium imports in 2024 still originated from China via third-country routing (notably Belgium), exposing the limits of outright bans when transshipment channels remain open. The structural vulnerability — no US gallium production, no strategic stockpile — has not changed.

Implication for photonics: InP and GaAs substrate suppliers remain exposed. Western foundries sourcing through Japanese and German intermediaries face cascading risk if Beijing tightens controls on those third-party channels.

CoWoS packaging: easing, but oligopolistic

CoWoS (Chip on Wafer on Substrate) — the advanced packaging technology enabling HBM integration in AI accelerators — was the primary supply chain bottleneck for AI hardware through 2024–2025. The picture in 2026 has shifted:

  • Capacity ramp: TSMC scaled CoWoS from ~35,000 wafers/month (late 2024) to ~75,000–80,000 wafers/month (end 2025), targeting 120,000–130,000 by end 2026.
  • Outsourcing begins: TSMC is offloading an estimated 240,000–270,000 wafers/year to OSATs — primarily Amkor (~180–190K) and SPIL (~60–80K) — marking the first time CoWoS production meaningfully exits TSMC.
  • Demand remains hyper-concentrated: NVIDIA (~60%), Broadcom (~15%), AMD (~11%) collectively lock in ~85%+ of total 2026 CoWoS supply. Less than 15% is available to all other buyers.

The bottleneck is loosening, but the market structure has not opened. For photonic chiplet developers seeking CoWoS-compatible packaging, scarcity has evolved from a technical constraint into a market access barrier — dominated by a handful of hyperscaler-adjacent chip companies with multi-year capacity reservations.

SOI wafer monoculture

Soitec controls approximately 80% of global SOI wafer supply via its SmartCut™ process IP. Unlike standard Si wafers (5 major suppliers), SOI has a single effective supplier. Any production disruption at Soitec propagates directly to every SiPh fab.

PDK fragmentation

Unlike CMOS, there is no standard SiPh process design kit shared across foundries. Each fab has proprietary component libraries — a design optimized for Tower's PD200 cannot be ported to GF45 without significant re-characterization. This slows ecosystem development and prevents the second-sourcing that mature supply chains depend on.

Supply Risk Legend

Critical
High
Developing
Bottleneck
Watch List

Disclaimer: This is research commentary, not financial advice. All investments carry risk.

Last reviewed: August 2026